Library Of EDA Utilities

EDAUtils builds the small, sharp utilities that SoC integration and verification teams keep rewriting by hand — RTL translators, netlist flatteners, testbench and register-model generators, parsers and checkers. Every tool runs in the browser here, or downloads as a standalone binary for your own flow.

AI-assisted parsing handles the messy real-world RTL that strict parsers reject, and each online run is queued, logged and emailed back to you when it finishes.

Translators & Converters
Verilog/VHDL Utilities
Generators & Parsers
Tool to convert Verilog into VHDL by keeping the same structure and function for ease of correlation.
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Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist.
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Generates VHDL testbench for a given entity along with random testvectors
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Tool to convert VHDL into Verilog by keeping the same structure and function for ease of correlation.
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Verilog Preprocessor to resolve macros like nested `ifdef , `define.
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Generates verilog testbench for a given module along with random testvectors
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Converts Liberty .lib Cells into empty verilog modules
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Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents in the higher level
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C Model generator from the IP-XACT Register Description
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Tool to convert IP-XACT into Verilog module
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Removes continuous assignment statements in a given netlist
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UVM Model generator from the IP-XACT Register Model
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Verilog to IP-XACT Component Generator.
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Create new hierarchy by grouping/combining selected instances.
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Verilog Document Generator from the RTL definition of an IP/SubSystem. Use DesignPlayer Hierarchy Brower to create hierarchy snapshot to review design
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Create Liberty .lib library from verilog module
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Verilog Hierarchy Removal Tool to ungroup all the instances in a given module
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Tool to generate Verilog wrapper by instantiating the specified module- flattens/splits multidimensional ports and SV interfaces while instantiating original module.
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Generates VHDL component from Verilog module definition.
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Uniquifies Verilog by prependin given prefix with modules, interfaces, classes, structures and their references.
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Tool to generate VHDL wrapper by instantiating the specified entity- flattens/splits multidimensional array and record type ports.
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Tool to convert Verilog into SystemC keeping the original structure as much as possible.
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Validate syntax and semantic of input IP-XACT file.
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Generate document from the IP-XACT Component/Register definition.
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Generates VHDL Entity from Verilog module definition.
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Validates IP-XACT Component ports and parameters with the corresponding Verilog Module ports and parameters.
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Generates connection database in JSON format from the Verilog SOC/SubSystem TOP.
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Generate TLM Model from IP-XACT File.
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Validates IP-XACT Component ports and parameters with the corresponding VHDL Entity ports and generics.
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Parses Veriog RTL and populates its object model which comes with a rich set of APIs to access design information.
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Tool to create IP-XACT Component definition from a VHDL Entity.
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Tool to compare the interfaces ( ports, generics ) between two VHDL entities.
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Parses synthesizable subset of VHDL and populates its object model which comes with a rich set of APIs to access design information.
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VHDL to SystemC translator which first converts the VHDL into Verilog and then converts the internal Verilog into SystemC.
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Tool to compare the ports, parameters, bus interfaces, registers between two IP-XACT files.
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Java based simple .lib parser, supports the widely used set of constructs.
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Tool to create VHDL Entity from IP-XACT Component.
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Tool to compare the interfaces ( ports, parameters, SV interfaces ) between two versions of a Verilog module or two similar modules.
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Parses Veriog Netlist and populates its object model which comes with a rich set of APIs to access design information.
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Convert IP-XACT Bus Interface definitions into System Verilog Interfaces.
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Compare SOC/Sub-System level connectivities between two revisions of the same- generate two connectivity JSON files and then compare them.
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Library to parse VCD file and populate datamodel and APIs to access the information and print it back.
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Converts IP-XACT Address Block file into XLSX for review and documentation purpose.
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Merges specific instances from different modules to one module.
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Generates HTML Documentation of Registers, both IP-Core and SOC Views
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Creates IP-XACT Address Block file from the legacy XLS/CSV based Register Management system.
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Utility to find instances or nets matching with the given regular expression as their names.
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Generates Verilog RTL from IP-XACT Register
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Upgrade old IP-XACT to new version- supported versions are 1.0, 1.2, 1.4, 1.5, 2009, 2014
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Sorts VHDL and Verilog files based upon dependencies
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Java based Unified Power Format, UPF parser, decompiler, comparator, validator, Object Model with Java and Tcl API
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EDAUtils capabilities in batch/commandline mode along with Tcl shell
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SOC Integration capabilities in batch/commandline mode along with Tcl shell
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Comprehensive IP-XACT capabilities in batch/commandline mode along with Tcl shell
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Pull up ports from sub-module to top by creating required new ports in all the intermediate hierarchies
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